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Figure 28 shows the RMII transmit and receive AC timing diagram.
REF_CLK
t RMXH
t RMX
t RMXF
t RMXR
TXD[1–0]
TX_EN
t RMTKHDX
RXD[1–0]
CRS_DV
Valid Data
RX_ER
t RMRDVKH
t RMRDXKH
Figure 28. RMII Transmit and Receive AC Timing
Figure 29 provides the AC test load.
Output
Z 0 = 50 Ω
R L = 50 Ω
V DDGE /2
Figure 29. AC Test Load
2.6.10.5
SMII AC Timing Specification
Table 44. SMII Mode Signal Timing
Characteristics
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge setup time
ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay
Notes:
1.
Typical REF_CLK clock period is 8ns
Symbol
t SMDVKH
t SMDXKH
t SMXR
Min
1.5
1.0
1.5
Max
—
—
5.0
Unit
ns
ns
ns
2.
3.
4.
Measured using a 5 pF load.
Measured using a 15 pF load
Program GCR4 as 0x00002008
Figure 30 shows the SMII Mode signal timing.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
57
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